The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.
A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.
