A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channel length and bias int o account.This is due to that the characteristics lenth significantly affects th e maximum lateral electric field and the length of velocity saturation region,bo th of which are very important in modeling the drain current and the substrate c urrent.The comparison between simulations and experiments shows a good predictio n of the model for submicron and deep-submicron LDD MOSFET.Moreover,the analyti cal model is suitable for descgn of devices as it is low in computation consumpt ion.
A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ections,yielding the gate bias dependent parameters,such as effective channel le ngth,parasitic resistance,and mobility,etc.This method avoids the gate bias rang e optimization,and retains the accuracy and simplicity of linear regression.The extracted gate bias dependent parameters are implemented in the compact I-V model which has been proposed for deep submicron LDD MOSFET's.The good agreemen ts between simulations and measurements of the devices on 0.18μm CMOS technolo gy indicate the effectivity of this technique.
For very high temperature annealing (1620℃) after ion implantation for 4H silicon carbide (4H SiC),the residual components of Al and O in the alundum furnace impact seriously on the surface of material,which yields the derivation of SiOC.This causes a significant degradation of the 4H SiC surface characteristics according to the results of surface composition analysis.As validity,Ni/SiC ohmic contact measurement illustrates a higher specific contact resistance than the normal value by a factor of 2～3.Consequently the MESFET fabricated with this kind of 4H SiC material results in a degraded I V output performance compared with that of normal 4H SiC MESFET.
A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.
