Two fabricated on-chip transformers under different ground conditions（i.e.,CG and IG types） have been measured to compare their different characteristics.With the aid of the electromagnetic（EM） solver,we have analyzed the differences from the electric and magnetic aspects,and different effects in these aspects can be described with the lumped capacitor and inductor from the perspective of the equivalent circuit model.A physicsbased equivalent circuit model is proposed to model transformers under different ground conditions.In addition, the simple parameter extraction procedure for the corresponding model is also provided.All the model parameters are extracted and agree with the analysis.In order to verify the model＇s validity and accuracy,we have compared the modeled and measured S-parameters,and an excellent agreement has been found over a broad frequency range.
A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.
A new compact model has been introduced to model on-chip spiral transformers.Unlike conventional models,which are often a compound of two spiral inductor models（i.e.,the combination of two coupledΠor 2-Πsub-circuits）,our new model only uses 12 elements to model the whole structure in the form of T topology.The new model is based on the physical meaning,and the process of model derivation is also presented.In addition,a simple parameter extraction procedure is proposed to get the elements＇ values without any fitting and optimization. In this procedure,a new method has been developed for the parameter extraction of the ladder circuit,which is commonly used to represent the skin effect.In order to verify the model＇s validity and accuracy,we have compared the simulated and measured self-inductance,quality factor,coupling coefficient and insertion loss,and an excellent agreement has been found over a broad frequency range up to the resonant frequency.
We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.
Fa-en LIUZhi-gong WANGZhi-qun LIQin LILu TANGGe-liang YANG
A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.
This paper focuses on a new design of a down-conversion mixer for a low-IF wideband receiver.Based on the folded structure and differential multiple gated transistor（DMGTR） technique,a novel quadrature mixer with a high conversion gain,a moderate linearity,and a moderate NF is proposed.The mixer is designed and implemented in a 0.18-m CMOS process,and can operate in a frequency range from 150 kHz to 1.5 GHz.The circuit performance is confirmed by both simulation and measurement results.The measurement results exhibit a peak conversion gain of 13.35 dB,a high third order input referred intercept point of 14.85 dBm,and a moderate single side band noise figure of 10.67 dB.Moreover,the whole quadrature mixer core occupies a compact die area of 0.122 mm2.It consumes a current of 3.96 mA（excluding the output buffers） under a single supply voltage of 1.8 V.
A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.
