To meet the demands for different supply voltage levels on SOC required by digital modules like CPU core and analog modules,a novel dual-output charge pump is proposed. The charge pump can output a step-up and a step-down voltage simultaneously with a high driving capability. The multiple gain pair technique was introduced to enhance its efficiency. The proposed co-use technology for capacitors and switch arrays reduced its cost. The charge pump was designed and fabricated in a TSMC 0.35μm mixed-signal CMOS process. A group of analytical equations were derived to model its static characteristics. A state-space model was derived to describe its small-signal dynamic behavior. Analytical predictions were verified by Spectre simulation and testing. The consistency of simulated results as well as test results with analytical predictions demonstrated the high precision of the derived analytical equations and the developed models.
To keep even current distribution among DC/DC converters in a paralleled power system,an automatic master-slave control （AMSC） current sharing scheme is presented,which was implemented by a current share control IC. A current feedback loop for output voltage adjustment is proposed for low signal distortion. Moreover,a special startup control logic is designed to improve startup timing and to speed up the initial current sharing. It was completed in 1.5μm bipolar-CMOS-DMOS （BCD） technology with an area of 3.6mm^2 . Using it,a paralleled power system of two DC/DC converters capable of outputting 12V/3A was built. Experimental results show that the current sharing error at full load is kept within 1%.
