This paper devoted to report the design and the achievement of an optical communication subsystem with 12 parallel channels in one chip.The system is capable of transmitting 10 Gbps bidirectional date over hundreds of meters.It can provide error detection and correction by using 8B/10B encoding and Cyclical Redundancy Checking (CRC) encoding when only single-channel fails.The design scheme has already passed the simulation in FPGA.This technique is useful to enhance the capability and the reliability of the very short reach (VSR) transmission systems.
CHEN Xiong-bin JIA Jiu-chun ZHOU Yi TANG Jun PEI Wei-hua LIU Bo CHEN Hong-da
We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor （MOS） capacitor configuration integrated into silicon-on-insulator （SOl）. Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure, which boosts the modulation efficiency compared with a single MOS capacitor. The simulation results demonstrate that the Vπ Lπ product is 2. 4V · cm. The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve, respectively,indicating a bandwidth of 8GHz. The phase shift efficiency and bandwidth can be enhanced by rib width scaling.
A novel silicon light emitting device was realized with standard 0.35μm 2P4M Mixed Mode/RF CMOS technology. The device functions in a reverse breakdown mode and can be turned on at 8.3 V and operated normally at a wide voltage range of 8.3 V-12.0 V. An output optical power of 13.6 nW was measured at the bias of 10 V and 100 mA, and the emitted light intensity was calculated to be more than 1 mW/cm2. The optical spectrum of the device is in the range of 500-820 nm.
LIU Hai-jun GU Ming LIU Jin-bin HUANG Bei-ju CHEN Hong-da
A pulse frequency modulation（PFM） circuit for retinal prosthesis,which generates electrical pulses with frequency proportional to the intensity of incident light, is presented. The fundamental characteristic of the circuit is described and analyzed. The circuit is realized in 0.6μm CMOS process,and the simulation results testify to the possibility of sub-retinal implantation.
