A new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion.It first estimates the routing congestion through a new routing model.Then,it formulates an integer linear programming (ILP) problem to determine cell flow direction and to avoid the conflictions between adjacent congestion areas.Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.
A global routing algorithm with performance optimization under multi constraints is proposed,which studies RLC coupling noise,timing performance,and routability simultaneously at global routing level.The algorithm is implemented and the global router is called CEE Gr.The CEE Gr is tested on MCNC benchmarks and the experimental results are promising.
An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
