A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput.
Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.
The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.
