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国家高技术研究发展计划(s2007AA01Z2A5)

作品数:2 被引量:1H指数:1
发文基金:国家自然科学基金国家高技术研究发展计划更多>>
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A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology
2010年
A MOS-NDR(negative differential resistance) transistor which is composed of four n-channel metaloxide -semiconductor field effect transistors(nMOSFETs) is fabricated in standard 0.35μm CMOS technology.This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD(resonant tunneling diode) in current-voltage characteristics.At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor,a flexible logic circuit is realized in this work,which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor.It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.
王伟黄北举董赞郭维廉陈弘达
1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications被引量:1
2009年
A zero-pole cancellation transimpedance amplifier(TIA)has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.
黄北举张旭陈弘达
关键词:CMOS
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