Phase change memory （PCM） has been regarded as a promising candidate for the next generation of nonvolatile memory. To decrease the power required to reset the PCM cell, titanium nitride （TIN） is preferred to be used as the bottom electrode of PCM due to its low thermal and suitable electrical conductivity. However, during the manufacture of PCM cell in 40 nm process node, abnormally high and discrete distribution of the resistance of TiN bottom electrode was found, which might be induced by the surface oxidation of TiN bottom electrode during the photoresist ashing process by oxygen plasma. In this work, we have studied the oxidation of TiN and found that with the increasing oxygen plasma ashing time, the thickness of the TiO2 layer became thicker and the state of the TiO2 layer changed from amorphous to crystalline, respectively. The resistance of TiN electrode contact chain with 4-5 nm TiO2 layer was confirmed to be almost three-orders of magnitude higher than that of pure TiN electrode, which led to the failure issue of PCM cell. We efficiently removed the oxidation TiO2 layer by a chemical mechanical polishing （CMP） process, and we eventually recovered the resistance of TiN bottom electrode from 1×10^5Ω/via back to 6×10^2 Ωvia and successfully achieved a uniform resistance distribution of the TiN bottom electrode.
The endurance characteristics of phase change memory are studied. With operational cycles, the resis- tances of reset and set states gradually change to the opposite direction. What is more, the operational conditions that are needed are also discussed. The thilure and the changes are concerned with the compositional change of the phase change material. An abnormal phenomenon that the threshold voltage decreases slightly at first and then increases is observed, which is due to the coaction of interthce contact and growing active volume size changing.
A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.
In this letter, a phase change random access memory(PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor(CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 m A, 100 and 10 ns,respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.
