A wavelet collocation method with nonlinear auto companding is proposed for behavioral modeling of switched current circuits.The companding function is automatically constructed according to the initial error distribution obtained through approximating the input output function of the SI circuit by conventional wavelet collocation method.In practical applications,the proposed method is a general purpose approach,by which both the small signal effect and the large signal effect are modeled in a unified formulation to ease the process of modeling and simulation.Compared with the published modeling approaches,the proposed nonlinear auto companding method works more efficiently not only in controlling the error distribution but also in reducing the modeling errors.To demonstrate the promising features of the proposed method,several SI circuits are employed as examples to be modeled and simulated.
In this paper, we present a SAT solver based on the combination of DPLL (Davis Putnam Logemann and Loveland) algorithm and Failed Literal Detection (FLD), one of the advanced reasoning techniques. We propose a Dynamic Filtering method that consists of two restriction rules for FLD: internal and external filtering. The method reduces the number of tested literals in FLD and its computational time while maintaining the ability to find most of the failed literals in each decision level. Unlike the pre-defined criteria, literals are removed dynamically in our approach. In this way, our FLD can adapt itself to different real-life benchmarks. Many useless tests are therefore avoided and as a consequence it makes FLD fast. Some other static restrictions are also added to further improve the efficiency of FLD. Experiments show that our optimized FLD is much more efficient than other advanced reasoning techniques.
